Switching between layer 2 switches as destination of IP packets from cards

ABSTRACT

A layer  2  switch switching circuit has two layer  2  switches of a redundant configuration and a plurality of cards for sending IP packets to each other through either one of the two layer  2  switches. Each of the two layer  2  switches has a state signal delivery unit for delivering a state signal representing whether the layer  2  switch is in an active state or a standby state. Each of the cards has a card controller for monitoring states of the two layer  2  switches based on state signals sent respectively from the two layer  2  switches, and switching between the two layer  2  switches as a destination of IP packets based on the monitored states.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a technology for switching between two layer 2 switches as a destination of IP packets from a plurality of cards of a base station apparatus which transmit IP packets through either one of the two layer 2 switches. A layer 2 switch refers to a switch for delivering an IP packet depending on the data of the IP packet in a layer 2 (data link layer).

2. Description of the Related Art

Generally, redundant configurations include a dual active system configuration having two systems both used as active systems and an active-backup system configuration having two systems used as an active system and a backup system, respectively. Active-backup system configurations are disclosed in JP-A-1999-246646, JP-A-1993-344144, JP-A-1997-135244, and JP-A-2003-234757 (hereinafter referred to as Documents 1 through 4, respectively).

Dual active and active-backup schemes need to be used differently depending on the system architecture that is involved. For example, a terminating unit for terminating a transmission path is generally installed in each transmission path. If a system architecture has a plurality of such transmission paths, then each transmission path with a terminating unit installed therein is used as an active system, and two such active systems are used as a dual active system configuration. If the system architecture has only one transmission path, then a plurality of terminating units are combined with the transmission path, and only the terminating units are provided in a redundant configuration. One of the terminating units belongs to an active system, and the other terminating units to a backup system, resulting in an active-backup system. Even the same system architecture needs to be compatible with either of the dual active system and the active-backup system depending on the transmission path or paths.

Layer 2 switches usually forward IP packets received from cards in a system to corresponding cards. The layer 2 switches also forward IP packets received from transmission paths to corresponding cards. Therefore, layer 2 switches may be mounted in terminating units. The layer 2 switches need to be compatible with either of the dual active system and the active-backup system.

The technologies disclosed in Documents 1 through 4 referred to above are related to active-backup system configurations, but not dual active system configurations. If a layer 2 switch that operates in an active system suffers a fault, then each card is required to switch the destination of IP packets to a layer 2 switch in another active system or a backup system. Heretofore, however, a dedicated device such as a controller disclosed in Document 4 is necessary for switching between layer 2 switches as a destination of IP packets.

A layer 2 switch includes therein a buffer for holding IP packets. When the destination of IP packets is switched from a layer 2 switch to another layer 2 switch, IP packets in the past remain held in the layer 2 switch which was active prior to the switching, tending to result in a packet loss. Such a packet loss may be eliminated by sending at all times replicas of IP packets to the layer 2 switch to which the destination of IP packets is switched. However, this process is subject to the danger of a duplication of IP packets during the switching.

Generally, IP networks are not supposed to guarantee a sequence of IP packets. However, if a sequence of IP packets is not guaranteed, then a receiver of the IP packets needs to perform some process of correcting the sequence in which the IP packets are received. A closed network in an apparatus, e.g., an IP network constructed only within an apparatus, can simplify the reception process of each card by guaranteeing a sequence of IP packets. Closed IP networks in apparatus are thus desirous of having layer 2 switches of a redundant configuration which are capable of guaranteeing a sequence of IP packets.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a layer 2 switch switching circuit, a base station apparatus, and a layer 2 switch switching method which are capable of switching between layer 2 switches as a destination of IP packets from each of cards without the need for a dedicated device, and which are compatible of both an active-backup system configuration and a dual active system configuration.

Another object of the present invention is to provide a layer 2 switch switching circuit, a base station apparatus, and a layer 2 switch switching method which are capable of preventing a packet loss, a duplication, and a scrambled sequence of IP packets when a destination of IP packets is switched from a layer 2 switch to another layer 2 switch.

A layer 2 switch switching circuit according to the present invention has two layer 2 switches of a redundant configuration and a plurality of cards for sending IP packets to each other through either one of the two layer 2 switches. Each of the two layer 2 switches has a state signal delivery unit for delivering a state signal representing whether the layer 2 switch is in an active state or a standby state. Each of the cards has a card controller for monitoring states of the two layer 2 switches based on state signals sent respectively from the two layer 2 switches, and switching between the two layer 2 switches as a destination of IP packets based on the monitored states.

With the above arrangement, even if one of the two layer 2 switches is put into the standby state when the two layer 2 switches are in the active state in a dual active system configuration, each of the cards is capable of automatically switching a destination of IP packets from the layer 2 switch which is put into the standby state to the layer 2 switch which is continuously in the active state. It is thus possible to switch from the active state of both the two layer 2 switches to the active state of one of the two layer 2 switches only.

Furthermore, when the two layer 2 switches are in an active-backup system configuration with one of them in the active state and the other in the standby state, if the layer 2 switch in an active system changes from the active state to the standby state, each of the cards can automatically switch the destination of IP packets from the layer 2 switch that is in the active state to the layer 2 switch that is in the standby state. Therefore, the two layer 2 switches can switch between the active system and the backup system.

As described above, regardless of whether the redundant configuration is either the dual active system configuration or the active-backup system configuration, the destination of IP packets from the cards can be switched without the need for a dedicated device which has heretofore been required. Since the destination of IP packets from the cards can be switched in either the dual active system configuration or the active-backup system configuration, the layer 2 switch switching circuit is highly flexible as it is compatible with both the dual active system configuration and the active-backup system configuration.

Each of the two layer 2 switches further includes an internal buffer and a switch controller. The internal buffer temporarily stores IP packets. The switch controller monitors the state of the other layer 2 switch based on the state signal delivered from the other layer 2 switch, stops sending IP packets to the corresponding card when a transition of the other layer 2 switch from the active state to the standby state is detected, and resumes sending IP packets to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.

With this arrangement, even when each of the layer 2 switches detects when the companion layer 2 switch changes from the active state to the standby state, it waits until the transmission of all the IP packets held by the internal buffer of the companion layer 2 switch is completed. Therefore, it is possible to prevent a packet loss from occurring which would be caused if past IP packets remain in the companion layer 2 switch. As a packet loss is prevented from occurring, it is not necessary to send at all times replicas of IP packets from the layer 2 switch from which the destination of IP packets is to be switched to the layer 2 switch to which the destination of IP packets is to be switched, and hence a duplication of IP packets is avoided. Furthermore, because each of the layer 2 switches resumes sending IP packets after the transmission of all the IP packets held by the internal buffer of the companion layer 2 switch is completed, the sequence of IP packets sent to cards is prevented from being scrambled.

If the switch controller receives IP packets from the cards while the switch controller is stopping sending IP packets to the corresponding card when the transition of the other layer 2 switch from the active state to the standby state is detected, the switch controller stores the received IP packets in the internal buffer. The switch controller resumes sending the IP packets stored in the internal buffer to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.

With this arrangement, each of the cards is capable of sending IP packets to the layer 2 switches even while the destination of IP packets is being changed. Inasmuch as there is no need to hold IP packets in each of the cards, each of the cards may be simplified in arrangement, and may be manufactured at a reduced cost.

The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a layer 2 switch switching circuit according to an embodiment of the present invention as it is incorporated in a dual active system;

FIG. 2 is a block diagram of the layer 2 switch switching circuit according to the embodiment of the present invention as it is incorporated in an active-backup system;

FIG. 3 is a block diagram of layer 2 switches shown in FIGS. 1 and 2;

FIG. 4 is a block diagram of switch managing circuits shown in FIGS. 1 and 2;

FIG. 5 is a block diagram of switching circuits shown in FIGS. 1 and 2;

FIG. 6 is a timing chart of an operation sequence of the layer 2 switch switching circuit according to the embodiment of the present invention as it is incorporated in the dual active system; and

FIG. 7 is a timing chart of an operation sequence of the layer 2 switch switching circuit according to the embodiment of the present invention as it is incorporated in the active-backup system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A layer 2 switch switching circuit according to an embodiment of the present invention is illustrated in FIGS. 1 and 2. The layer 2 switch switching circuit illustrated in FIG. 1 and the layer 2 switch switching circuit illustrated in FIG. 2 are identical in structure with each other. However, FIG. 1 shows the layer 2 switch switching circuit as it is incorporated in a dual active system, and FIG. 2 shows the layer 2 switch switching circuit as it is incorporated in an active-backup system.

As shown in FIGS. 1 and 2, the layer 2 switch switching circuit according to the embodiment of the present invention has a plurality of cards (#A through #C) 100 _(A) through 100 _(C), logic processor (#0) 200 ₀ and physical processor (#0) 300 ₀ belonging to system 0, logic processor (#1) 200 ₁ and physical processor (#1) 300 ₁ belonging to system 1, and process setting switch 700. The layer 2 switch switching circuit is installed in a wireless or wired base station apparatus.

Though only three cards (#A through #C) 100 _(A) through 100 _(C) are illustrated in FIGS. 1 and 2, the number of cards is not limited insofar as a plurality of cards are employed. Physical processors (#0, #1) 200 ₀, 300 ₁ comprise cards that are generally referred to as physical layer cards. However, these physical processors will be referred to as physical processors in order to avoid confusion with cards (#A through #C) 100 _(A) through 100 _(C). Similarly, logic processors (#0, #1) 200 ₀, 200 ₁ comprise cards that are generally referred to as highway cards, and will be referred to as logic processors.

The layer 2 switch switching circuit according to the embodiment of the present invention is of a redundant configuration including system 0 and system 1, and is capable of operating in a full active system configuration wherein both system 0 and system 1 are active systems and an active-dual system configuration wherein one of system 0 and system 1 is an active system and the other a backup system. IP packets are used to transmit information between cards (#A through #C) 100 _(A) through 100 _(C). Layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ are duplexed and provided in logic processors (#0, #1) 200 ₀, 200 ₁, respectively. All IP packets are delivered through either one of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁.

Physical processor (#0) 300 ₀ is connected to optical fiber transmission path (#0) 601 ₀ as an external link of system 0. Physical processor (#0) 300 ₀ has switching circuit (#0) 310 ₀ and photoelectric transducer circuit (#0) 320 ₀. Photoelectric transducer circuit (#0) 320 ₀ converts an IP packet transmitted as an optical signal through optical fiber transmission path (#0) 601 ₀ into an electric signal. Switching circuit (#0) 310 ₀ switches the destination of the IP packet as the electric signal from photoelectric transducer circuit (#0) 310 ₀ to either logic processor (#0) 200 ₀ only or both logic processor (#0) 200 ₀ and companion physical processor (#1) 300 ₁. Switching circuit (#0) 310 ₀ also switches the destination of an IP packet from logic processor (#0) 200 ₀ to either photoelectric transducer circuit (#0) 320 ₀ only or both photoelectric transducer circuit (#0) 320 ₀ and companion physical processor (#1) 300 ₁. Photoelectric transducer circuit (#0) 320 ₀ also converts an IP packet sent as an electric signal from switching circuit (#0) 310 ₀ into an optical signal, and outputs the IP packet as the optical signal to optical fiber transmission path (#0) 601 ₀.

Logic processor (#0) 200 ₀ has layer 2 switch SW (#0) 210 ₀, switch managing circuit (#0) 220 ₀, and network processor (#0) 230 ₀. Network processor (#0) 230 ₀ converts an IP packet from physical processor (#0) 300 ₀ into a packet format for use in the layer 2 switch switching circuit. Layer 2 switch SW (#0) 210 ₀ delivers the packet from network processor (#0) 230 ₀ to a corresponding one of cards (#A through #C) 100 _(A) through 100 _(C). Switch managing circuit (#0) 220 ₀ outputs a state instruction signal for putting layer 2 switch SW (#0) 210 ₀ into an active state or a standby state to layer 2 switch SW (#0) 210 ₀. Layer 2 switch SW (#0) 210 ₀ also delivers packets from cards (#A through #C) 100 _(A) through 100 _(C) to corresponding cards, and outputs them to network processor (#0) 230 ₀. Network processor (#0) 230 ₀ also converts a packet from layer 2 switch SW (#0) 210 ₀, which is in the packet format for use in the layer 2 switch switching circuit, to an IP packet of the original format, and sends the IP packet to physical processor (#0) 300 ₀.

Similarly, physical processor (#1) 300 ₁ is connected to optical fiber transmission path (#1) 601 ₁ as an external link of system 1. Physical processor (#1) 300 ₁ has switching circuit (#1) 310 ₁ and photoelectric transducer circuit (#1) 320 ₁. Photoelectric transducer circuit (#1) 320 ₁ converts an IP packet transmitted as an optical signal through optical fiber transmission path (#1) 601 ₁ into an electric signal. Switching circuit (#1) 310 ₁ switches the destination of the IP packet as the electric signal from photoelectric transducer circuit (#1) 320 ₁ to either logic processor (#1) 200 ₁ only or both logic processor (#1) 200 ₁ and companion physical processor (#0) 300 ₀. Switching circuit (#1) 310 ₁ also switches the destination of an IP packet from logic processor (#1) 200 ₁ to either photoelectric transducer circuit (#1) 320 ₁ only or both photoelectric transducer circuit (#1) 320 ₁ and companion physical processor (#0) 300 ₀. Photoelectric transducer circuit (#1) 320 ₁ also converts an IP packet sent as an electric signal from switching circuit (#1) 310 ₁ into an optical signal, and outputs the IP packet as the optical signal to optical fiber transmission path (#1) 601 ₁.

Logic processor (#1) 200 ₁ has layer 2 switch SW (#1) 210 ₁, switch managing circuit (#1) 220 ₁, and network processor (#1) 230 ₁. Network processor (#1) 230 ₁ converts an IP packet from physical processor (#1) 300 ₁ into a packet format for use in the layer 2 switch switching circuit. Layer 2 switch SW (#1) 210 ₁ delivers the packet from network processor (#1) 230 ₁ to a corresponding one of cards (#A through #C) 100 _(A) through 100 _(C). Switch managing circuit (#1) 220 ₁ outputs a state instruction signal for putting layer 2 switch SW (#1) 210 ₁ into an active state or a standby state to layer 2 switch SW (#1) 210 ₁. Layer 2 switch SW (#1) 210 ₁ also delivers packets from cards (#A through #C) 100 _(A) through 100 _(C) to corresponding cards, and outputs them to network processor (#1) 230 ₁. Network processor (#1) 230 ₁ also converts a packet from layer 2 switch SW (#1) 210 ₁, which is in the packet format for use in the layer 2 switch switching circuit, to an IP packet of the original format, and sends the IP packet to physical processor (#1) 300 ₁.

As shown in FIG. 3, layer 2 switch SW (#0) 210 ₀ has switch controller 211 ₀, internal buffer 212 ₀, state signal delivery unit 213 ₀, and buffer state signal delivery unit 214 ₀. Based on a state instruction signal from switch managing circuit (#0) 220 ₀, state signal delivery unit 213 ₀ delivers a state signal indicative of whether it is in an active state or a standby state to signal line SW_CONT#0B 501 ₀. If state signal delivery unit 213 ₀ is in the active state (ACT), then it sets the state signal to logic “0”. Internal buffer 212 ₀ temporarily stores IP packets from cards (#A through #C) 100 _(A) through 100 _(C) and network processor (#0) 230 ₀. Buffer state signal delivery unit 214 ₀ delivers a buffer state signal indicative of whether internal buffer 212 ₀ stores an IP packet or not to signal line SW_EMP#0B 502 ₀. If internal buffer 212 ₀ is empty, then buffer state signal delivery unit 214 ₀ sets the buffer state signal to logic “1”. Switch controller 211 ₀ controls layer 2 switch SW (#0) 210 ₀ in its entirety.

Layer 2 switch SW (#1) 210 ₁ has switch controller 211 ₁, internal buffer 212 ₁, state signal delivery unit 213 ₁, and buffer state signal delivery unit 214 ₁. Based on a state instruction signal from switch managing circuit (#1) 220 ₁, state signal delivery unit 213 ₁ delivers a state signal indicative of whether it is in an active state or a standby state to signal line SW_CONT#1B 501 ₁. If state signal delivery unit 213 ₁ is in the active state (ACT), then it sets the state signal to logic “0”. Internal buffer 212 ₁ temporarily stores IP packets from cards (#A through #C) 100 _(A) through 100 _(C) and network processor (#1) 230 ₁. Buffer state signal delivery unit 214 ₁ delivers a buffer state signal indicative of whether internal buffer 212 ₁ stores an IP packet or not to signal line SW_EMP#1B 502 ₁. If internal buffer 212 ₁ is empty, then buffer state signal delivery unit 214 ₁ sets the buffer state signal to logic “1”. Switch controller 211 ₁ controls layer 2 switch SW (#1) 210 ₁ in its entirety.

Signal line SW_CONT#0B 501 ₀ is connected to companion layer 2 switch SW (#1) 210 ₁, and signal line SW_CONT#1B 501 ₁ is connected to companion layer 2 switch SW (#0) 210 ₀. Therefore, layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ are capable of monitoring the states of the companion layer 2 switches. Signal lines SW_CONT#0B 501 ₀, SW_CONT#1B 501 ₁ are connected to all cards (#A through #C) 100 _(A) through 100 _(C). Therefore, cards (#A through #C) 100 _(A) through 100 _(C) are capable of monitoring the states of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁. When sending IP packets, cards (#A through #C) 100 _(A) through 100 _(C) thus can determine which one of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ they should send IP packets to.

Signal SW_EMP#1B 502 ₁ is connected to layer 2 switch SW (#0) 210 ₀. Therefore, layer 2 switch SW (#0) 210 ₀ is capable of monitoring the state of internal buffer 212 ₁ of companion layer 2 switch SW (#1) 210 ₁. Signal SW_EMP#0B 502 ₀ is connected to layer 2 switch SW (#1) 210 ₁. Therefore, layer 2 switch SW (#1) 210 ₁ is capable of monitoring the state of internal buffer 212 ₀ of companion layer 2 switch SW (#0) 210 ₀.

In FIGS. 1 and 2, each of cards (#A through #C) 100 _(A) through 100 _(C) comprises a card referred to as a call processing control card, a baseband processing card, a transmission/reception card, or a monitoring control card in a wireless base station apparatus or the like. Each of cards (#A through #C) 100 _(A) through 100 _(C) is connected to Ethernet links 401 ₀, 402 ₀, and send IP packets to and receive IP packets from layer 2 switch SW (#0) 210 ₀ through Ethernet links 401 ₀, 402 ₀. Each of cards (#A through #C) 100 _(A) through 100 _(C) is also connected to Ethernet links 401 ₁, 402 ₁, and send IP packets to and receive IP packets from layer 2 switch SW (#1) 210 ₁ through Ethernet links 401 ₁, 402 ₁.

Each of cards (#A through #C) 100 _(A) through 100 _(C) has card controller 101 serving as a CPU (Central Processing Unit), MAC (Media Access Control) circuits 102, 104, and PHY (PHYsical layer) circuits 103, 105. PHY circuit 103 and MAC circuit 102 correspond respectively to Ethernet links 401 ₀, 402 ₀, and PHY circuit 105 and MAC circuit 104 correspond respectively to Ethernet links 401 ₁, 402 ₁. Card controller 101 is connected to two MAC circuits 102, 104 and sends and receives IP packets through one or both of MAC circuits 102, 104. Each of PHY circuits 103, 105 comprises an LSI (Large Scale Integration) circuit for detecting data in layer 1 at the front end of an IP packet. Each of MAC circuits 102, 104 comprises an LSI circuit for analyzing the destination of an IP packet based on data in layer 2 of the IP packet, correcting errors of IP packets, and managing MAC addresses.

Process setting switch 700 is a switch for setting the layer 2 switch switching circuit to either an active-backup system configuration or a dual active system configuration. Process setting switch 700 is manually operated by the user. Process setting switch 700 applies its logic output signal to switch managing circuit (#0) 220 ₀ of logic processor (#0) 200 ₀, switch managing circuit (#1) 220 ₁ of logic processor (#1) 200 ₁, switching circuit (#0) 310 ₀ of physical processor (#0) 300 ₀, and switching circuit (#1) 310 ₁ of physical processor (#1) 300 ₁.

In the example shown in FIG. 1, the layer 2 switch switching circuit is set to the dual active system configuration by process setting switch 700, and is connected to both optical fiber transmission path (#0) 601 ₀ and optical fiber transmission path (#1) 601 ₁ which serve as active system links. In the present example, an IP packet transmitted as an optical signal through optical fiber transmission path (#0) 601 ₀ is converted by photoelectric transducer circuit (#0) 320 ₀ of physical processor (#0) 300 ₀ into an electric signal, which is output from switching circuit (#0) 310 ₀ to logic processor (#0) 200 ₀. An IP packet transmitted as an optical signal through optical fiber transmission path (#1) 601 ₁ is converted by photoelectric transducer circuit (#1) 320 ₁ of physical processor (#1) 300 ₁ into an electric signal, which is output from switching circuit (#1) 310 ₁ to logic processor (#1) 200 ₁.

In the example shown in FIG. 2, the layer 2 switch switching circuit is set to the active-backup system configuration by process setting switch 700, and is connected to optical fiber transmission path (#0) 601 ₀ only which serves as an active system link. In the present example, an IP packet transmitted as an optical signal through optical fiber transmission path (#0) 601 ₀ is converted by photoelectric transducer circuit (#0) 320 ₀ of physical processor (#0) 300 ₀ into an electric signal, which is distributed from switching circuit (#0) 310 ₀ to logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁. Since either one of logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁ is necessarily in the active state and the other in the standby state in the active-backup system configuration, duplicated IP packets will not be delivered to a corresponding card.

Switch managing circuits (#0, #1) 220 ₀, 220 ₁ of logic processors (#0, #1) 200 ₀, 200 ₁ and switching circuits (#0, #1) 310 ₀, 310 ₁ of physical processors (#0, #1) 300 ₀, 300 ₁ will be described in detail below.

First, switch managing circuits (#0, #1) 220 ₀, 220 ₁ will be described below with reference to FIG. 4.

As shown in FIG. 4, switch managing circuit (#0) 220 ₀ has NAND gate 221 ₀, NAND gate 222 ₀, selector 223 ₀, and pull-up resistor 224 ₀.

NAND gate 221 ₀ has an output terminal connected to switch managing circuit (#1) 220 ₁ of logic processor (#1) 200 ₁. NAND gate 221 ₀ has input terminals for being supplied with a reset signal which indicates resetting when it is of logic “0”, an alarm signal which indicates the generation of an alarm when it is of logic “0”, a closure signal which indicates a closure state when it is of logic “0”, a pulse signal which represents a negative pulse when logic processor (#0) 200 ₀ is switched from the active system to the backup system, and an output signal from selector 223 ₀. NAND gate 221 ₀ applies an output signal as a state instruction signal, which represents the active state when it is “0” and the standby state when it is “1”, also to layer 2 switch SW (#0) 210 ₀.

Selector 223 ₀ is a circuit for selecting a signal from input terminal X or a signal from input terminal Y based on a signal from process setting switch 700. Specifically, selector 223 ₀ selects the signal from input terminal X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration, and selects the signal from input terminal Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration.

NAND gate 222 ₀ has input terminals for being supplied with the output signal from NAND gate 221 ₀ and a closure canceling signal which indicates the cancellation of the closure state when it is of logic “0”. NAND gate 222 ₀ has an output terminal connected to input terminal X of selector 223 ₀. Input terminal Y of selector 223 ₀ is connected to the output terminal of NAND gate 221 ₁ of switch managing circuit (#1) 220 ₁. Pull-up resistor 224 ₀ is connected to input terminal Y of selector 223 ₀.

The alarm signal input to NAND gate 221 ₀ is generated by an alarm detecting circuit (not shown) in the layer 2 switch switching circuit. The reset signal, the closure signal, and the pulse signal that are input to NAND gate 221 ₀, and the closure canceling signal input to NAND gate 222 ₀ are signals that are generated when the user manually operates switches (not shown). For example, the user places logic processor (#0) 200 ₀ into the closure state when logic processor (#0) 200 ₀ is to be serviced for maintenance.

Similarly, switch managing circuit (#0) 220 ₁ has NAND gate 221 ₁, NAND gate 222 ₁, selector 223 ₁, and pull-up resistor 224 ₁.

NAND gate 221 ₁ has an output terminal connected to switch managing circuit (#0) 220 ₀ of logic processor (#0) 200 ₀. NAND gate 221 ₁ has input terminals for being supplied with a reset signal which indicates resetting when it is of logic “0”, an alarm signal which indicates the generation of an alarm when it is of logic “0”, a closure signal which indicates a closure state when it is of logic “0”, a pulse signal which represents a negative pulse when logic processor (#1) 200 ₁ is switched from the active system to the backup system, and an output signal from selector 223 ₁. NAND gate 221 ₁ applies an output signal as a state instruction signal, which represents the active state when it is “0” and the standby state when it is “1”, also to layer 2 switch SW (#1) 210 ₁.

Selector 223 ₁ is a circuit for selecting a signal from input terminal X or a signal from input terminal Y based on a signal from process setting switch 700. Specifically, selector 223 ₁ selects the signal from input terminal X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration, and selects the signal from input terminal Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration.

NAND gate 222 ₁ has input terminals for being supplied with the output signal from NAND gate 221 ₁ and a closure canceling signal which indicates the cancellation of the closure state when it is of logic “0”. NAND gate 222 ₁ has an output terminal connected to input terminal X of selector 223 ₁. Input terminal Y of selector 223 ₁ is connected to the output terminal of NAND gate 221 ₀ of switch managing circuit (#0) 220 ₀. Pull-up resistor 224 ₁ is connected to input terminal Y of selector 223 ₁.

The alarm signal input to NAND gate 221 ₁ is generated by an alarm detecting circuit (not shown) in the layer 2 switch switching circuit. The reset signal, the closure signal, and the pulse signal that are input to NAND gate 221 ₁, and the closure canceling signal input to NAND gate 222 ₁ are signals that are generated when the user manually operates switches (not shown). For example, the user places logic processor (#1) 200 ₁ into the closure state when logic processor (#1) 200 is to be serviced for maintenance.

Switching circuits (#0, #1) 310 ₀, 310 ₁ will be described below with reference to FIG. 5.

As shown in FIG. 5, switching circuit (#0) 310 ₀ has selector 311 ₀, OR circuit 312 ₀, selector 313 ₀, and OR circuit 314 ₀.

Input terminal of selector 311 ₀ is supplied with an IP packet from photoelectric transducer circuit (#0) 320 ₀. Selector 311 ₀ has two input terminals, i.e., input terminal X and input terminal Y. Based on a signal from processing setting switch 700, selector 311 ₀ selects either one of signals from input terminal X and input terminal Y. Specifically, selector 311 ₀ selects the signal from input terminal X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration, and selects the signal from input terminal Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration. Selector 311 ₀ transfers an IP packet input through input terminal X or input terminal Y to logic processor (#0) 200 ₀. An IP packet from logic processor (#0) 200 ₀ is input to input terminal X of selector 313 ₀. Selector 313 ₀ has two input terminals, i.e., input terminal X and input terminal Y. Based on a signal from processing setting switch 700, selector 313 ₀ selects either one of signals from input terminal X and input terminal Y. Specifically, selector 313 ₀ selects the signal from input terminal X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration, and selects the signal from input terminal Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration. Selector 313 ₀ transfers an IP packet input through input terminal X or input terminal Y to photoelectric transducer circuit (#0) 320 ₀.

OR circuit 312 ₀ ORs an IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and an IP packet signal from photoelectric transducer circuit (#1) 320 ₁, and inputs a resultant output signal to input terminal Y of selector 311 ₀. OR circuit 314 ₀ ORs an IP packet signal from logic processor (#0) 200 ₀ and an IP packet signal from logic processor (#1) 200 ₁, and inputs a resultant output signal to input terminal Y of selector 313 ₀.

Likewise, switching circuit (#1) 310 ₁ has selector 311 ₁, OR circuit 312 ₁, selector 313 ₁, and OR circuit 314 ₁.

An IP packet from photoelectric transducer circuit (#1) 320 ₁ is supplied to input terminal X of selector 311 ₁ of switching circuit (#1) 310 ₁. Selector 311 ₁ has two input terminals, i.e., input terminal X and input terminal Y. Based on a signal from processing setting switch 700, selector 311 ₁ selects either one of signals from input terminal X and input terminal Y. Specifically, selector 311 ₁ selects the signal from input terminal X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration, and selects the signal from input terminal Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration. Selector 311 ₁ transfers an IP packet input through input terminal X or input terminal Y to logic processor (#1) 200 ₁. An IP packet from logic processor (#1) 200 ₁ is input to input terminal X of selector 313 ₁. Selector 313 ₁ has two input terminals, i.e., input terminal X and input terminal Y. Based on a signal from processing setting switch 700, selector 313 ₁ selects either one of signals from input terminal X and input terminal Y. Specifically, selector 313 ₁ selects the signal from input terminal X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration, and selects the signal from input terminal Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration. Selector 313 ₁ transfers an IP packet input through input terminal X or input terminal Y to photoelectric transducer circuit (#1) 320 ₁.

OR circuit 312 ₁ ORs an IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and an IP packet signal from photoelectric transducer circuit (#1) 320 ₁, and inputs a resultant output signal to input terminal Y of selector 311 ₁. OR circuit 314 ₁ ORs an IP packet signal from logic processor (#0) 200 ₀ and an IP packet signal from logic processor (#1) 200 ₁, and inputs a resultant output signal to input terminal Y of selector 313 ₁.

Operation of the layer 2 switch switching circuit according to the present embodiment will be described below. Specifically, operation of the layer 2 switch switching circuit as it is incorporated in the dual active system, and operation of the layer 2 switch switching circuit as it is incorporated in the active-backup system will be described below.

(A) Operation of the Layer 2 Switch Switching Circuit as it is incorporated in the Dual Active System:

Operation of Switch Managing Circuits (#0, #1) 220 ₀, 220 ₁:

Operation of switch managing circuits (#0, #1) 220 ₀, 220 ₁ when the layer 2 switch switching circuit is incorporated in the dual active system will be described below with reference to FIGS. 1 and 4.

Selector 223 ₀ of switch managing circuit (#0) 220 ₀ and selector 223 ₁ of switch managing circuit (#1) 220 ₁ select respective input terminals X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration. Since signals that have connected switch managing circuit 220 ₀ and switch managing circuit 220 ₁ to each other are no longer applied, switch managing circuit 220 ₀ and switch managing circuit 220 ₁ are independent of each other.

In switch managing circuit 220 ₀, the output signal from NAND gate 221 ₀ is delivered through NAND gate 222 ₀ back to an input terminal of NAND gate 221 ₀. Therefore, NAND gate 221 ₀ and NAND gate 222 ₀ jointly make up a flip-flop. The output signal from NAND gate 221 ₀ is initially of logic “0”, putting layer 2 switch SW (#0) 210 ₀ into the active state. In this state, it is assumed that either one of the input signals applied to NAND gate 221 ₀ is of logic “0” when the reset signal is set to logic “0” by the user, or the alarm signal is set to logic “0” by the generation of an alarm, or the closure signal is set to logic “0” by the closure state set by the user. Since the output signal from NAND gate 221 ₀ becomes logic “1”, layer 2 switch SW (#0) 210 ₀ changes to the standby state. If the closure state is canceled by the user to set the closure canceling signal to logic “0”, the flip-flop changes from one state to the other, setting the output signal from NAND gate 221 ₀ to logic “0”, so that layer 2 switch SW (#0) 210 ₀ changes to the active state. According to the dual active system configuration, the pulse signal which goes negative upon switching from the active system to the backup system is not employed, but the closure signal or the closure canceling signal is manually controlled to change layer 2 switch SW (#0) 210 ₀ to the active state or the standby state. When an alarm is generated, since logic level “0” of the alarm signal is input to the corresponding input terminal of NAND gate 221 ₀, layer 2 switch SW (#0) 210 ₀ automatically changes to the standby state.

Similarly, in switch managing circuit 220 ₁, the output signal from NAND gate 221 ₁ is delivered through NAND gate 222 ₁ back to an input terminal of NAND gate 221 ₁. Therefore, NAND gate 221 ₁ and NAND gate 222 ₁ jointly make up a flip-flop. The output signal from NAND gate 221 ₁ is initially of logic “0”, putting layer 2 switch SW (#1) 210 ₁ into the active state. In this state, it is assumed that either one of the input signals applied to NAND gate 221 ₁ is of logic “0” when the reset signal is set to logic “0” by the user, or the alarm signal is set to logic “0” by the generation of an alarm, or the closure signal is set to logic “0” by the closure state set by the user. Since the output signal from NAND gate 221 ₁ becomes logic “1”, layer 2 switch SW (#1) 210 ₁ changes to the standby state. If the closure state is canceled by the user to set the closure sure canceling signal to logic “0”, the flip-flop changes from one state to the other, setting the output signal from NAND gate 221 ₁ to logic “0”, so that layer 2 switch SW (#1) 210 ₁ changes to the active state. According to the dual active system configuration, the pulse signal which goes negative upon switching from the active system to the backup system is not employed, but the closure signal or the closure canceling signal is manually controlled to change layer 2 switch SW (#1) 210 ₁ to the active state or the standby state. When an alarm is generated, since logic level “0” of the alarm signal is input to the corresponding input terminal of NAND gate 221 ₁, layer 2 switch SW (#1) 210 ₁ automatically changes to the standby state.

Operation of Switching Circuits (#0, #1) 310 ₀, 310 ₁:

Operation of switching circuits (#0, #1) 310 ₀, 310 ₁ when the layer 2 switch switching circuit is incorporated in the dual active system will be described below with reference to FIGS. 1 and 5.

Selectors 311 ₀, 313 ₀ of switching circuit (#0) 310 ₀ and selectors 311 ₁, 313 ₁ of switching circuit (#1) 310 ₁ select respective input terminals X when process setting switch 700 sets the layer 2 switch switching circuit to the dual active system configuration.

In switching circuit (#0) 310 ₀, an IP packet from photoelectric transducer circuit (#0) 320 ₀ passes through selector 311 ₀ and is output to logic processor (#0) 200 ₀, and an IP packet from logic processor (#0) 200 ₀ passes through selector 313 ₀ and is output to photoelectric transducer circuit (#0) 320 ₀.

Similarly, in switching circuit (#1) 310 ₁, an IP packet from photoelectric transducer circuit (#1) 320 ₁ passes through selector 311 ₁ and is output to logic processor (#1) 200 ₁, and an IP packet from logic processor (#1) 200 ₁ passes through selector 313 ₁ and is output to photoelectric transducer circuit (#1) 320 ₁.

Thus, logic processor (#0) 200 ₀ is connected to physical processor (#0) 300 ₀ and operates in the active system, and logic processor (#1) 200 ₁ is connected to physical processor (#1) 300 ₁ and operates in the active system. Therefore, the layer 2 switch switching circuit operates in the dual active system.

Operation of Layer 2 Switches SW (#0, #1) 210 ₀, 210 ₁ and cards (#A Through #C) 100 _(A) Through 100 _(C):

Operation of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ and cards (#A through #C) 100 _(A) through 100 _(C) when the layer 2 switch switching circuit is incorporated in the dual active system will be described below with reference to FIGS. 1, 3, and 6. For the sake of brevity, only operation of cards (#A, #B) 100 _(A), 100 _(B) will be described below.

Both layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ are in the active state (ACT), and signals on both signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁ are active. The signals on signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁ are active when they are of logic “0” and inactive when they are of logic “1”.

It is assumed that an alarm is generated due to a fault or the closure state is set by the user in either one of logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁. In the logic processor wherein the fault occurs or the closure state is set, the switch managing circuit generates a state instruction signal representing the standby state, placing the layer 2 switch into the standby state (STBY). Specifically, one of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ is in the standby state (STBY) and the other in the active state (ACT), so that all IP packets will pass through only the layer 2 switch in the active state (ACT).

Operation of the layer 2 switch switching circuit upon a transition from the active state of both layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ to the standby state of only layer 2 switch SW (#0) 210 ₀ will be described below. It is assumed that when both layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ are in the active state (ACT), i.e., both state signal delivery unit 213 ₀ and state signal delivery unit 213 ₁ are delivering active signals to signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁, operational conditions are as follows: In order to distribute loads of IP packets, the destination of IP packets from each of cards (#A, #B) 100 _(A), 100 _(B) is determined by default as either one of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁. Card controller 101 of each of cards (#A, #B) 100 _(A), 100 _(B) sends IP packets to the default destination. For example, a card that is positioned as an even-numbered card from the left (or right) has layer 2 switch SW (#0) 210 ₀ as the destination of IP packets, and a card that is positioned as an odd-numbered card from the left (or right) has layer 2 switch SW (#1) 210 ₁ as the destination of IP packets. When layer 2 switch SW (#0) 210 ₀ is in the standby state and layer 2 switch SW (#1) 210 ₁ is in the active state, card controller 101 of each of cards (#A, #B) 100 _(A), 100 _(B) unconditionally sends IP packets to layer 2 switch SW (#1) 210 ₁.

Operation of the layer 2 switch switching circuit if only layer 2 switch SW (#0) 210 ₀ is switched to the standby state when both layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ have been in the active state in the dual active system configuration will be described below with reference to the timing chart shown in FIG. 6.

Prior to time T1, both layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ are in the active state (ACT). Therefore, both state signal delivery unit 213 ₀ and state signal delivery unit 213 ₁ are delivering active signals to signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁. Buffer state signal delivery unit 214 ₀ is delivering a signal indicating that internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ is holding IP packets to signal line SW_EMP#0B 502 ₀. At this time, the signal on signal line SW_EMP#0B 502 ₀ is of logic “0”. Card controller 101 of card (#A) 100 _(A) is sending IP packets to layer 2 switch SW (#0) 210 ₀ which is the default destination, and card controller 101 of card (#B) 100 _(B) is sending IP packets to layer 2 switch SW (#1) 210 ₁ which is the default destination. Switch controller 211 ₀ of layer 2 switch SW (#0) 210 ₀ and switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ are sending IP packets to a corresponding one of card (#A) 100 _(A) and card (#B) 100 _(B).

When the user sets logic processor (#0) 200 ₀ to the closure state at time T1, a state instruction signal indicative of a transition to the standby state is input from switch managing circuit (#0) 220 ₀ to layer 2 switch SW (#0) 210 ₀. Then, state signal delivery unit 213 ₀ of layer 2 switch SW (#0) 210 ₀ immediately makes the signal on signal line SW_CONT#0B 501 ₀ inactive.

Between time T1 and time T2, in response to the inactive signal on signal line SW_CONT#0B 501 ₀, card controller 101 of card (#A) 100 _(A) monitors signal line SW_CONT#1B 501 ₁. Since the signal on signal line SW_CONT#1B 501 ₁ is active, card controller 101 of card (#A) 100 _(A) sends IP packets to layer 2 switch SW (#1) 210 ₁. Card controller 101 of card (#B) 100 _(B) continuously sends IP packets to layer 2 switch SW (#1) 210 ₁.

Switch controller 211 ₀ of layer 2 switch SW (#0) 210 ₀ continuously sends IP packets held by internal buffer 212 ₀ until it completes the transmission of all the IP packets held by internal buffer 212 ₀. When switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ detects the transition of layer 2 switch SW (#0) 210 ₀ to the standby state based on the state signal on signal line SW_CONT#0B 501 ₀, switch controller 211 ₁ accepts IP packets from card (#A) 100 _(A) and card (#B) 100 _(B) and holds them in internal buffer 212 ₁, but stops sending IP packets to card (#A) 100 _(A) and card (#B) 100 _(B). Switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ monitors signal line SW_EMP#0B 502 ₀, and waits until the transmission of all the IP packets held by internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ is completed and internal buffer 212 ₀ becomes empty. When internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ is empty, the signal on signal line SW_EMP#0B 502 ₀ becomes logic “1”.

When internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ becomes empty at time T2, switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ resumes sending IP packets held by internal buffer 212 ₁. At this time, layer 2 switch SW (#0) 210 ₀ completely changes to the standby state (STBY).

(B) Operation of the Layer 2 Switch Switching Circuit as it is Incorporated in the Active-Dual System:

Operation of Switch Managing Circuits (#0, #1) 220 ₀, 220 ₁:

Operation of switch managing circuits (#0, #1) 220 ₀, 220 ₁ when the layer 2 switch switching circuit is incorporated in the active-backup system will be described below with reference to FIGS. 2 and 4.

Selector 223 ₀ of switch managing circuit (#0) 220 ₀ and selector 223 ₁ of switch managing circuit (#1) 220 ₁ select respective input terminals Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration.

The output signal from NAND gate 221 ₀ is input through selector 223 ₁ to NAND gate 221 ₁, and the output signal from NAND gate 221 ₁ is input through selector 223 ₀ to NAND gate 221 ₀. Therefore, NAND gate 221 ₀ and NAND gate 221 ₁ jointly make up a flip-flop. Since the output signal from NAND gate 221 ₀ and the output signal from NAND gate 221 ₁ correspond to output signals of the flip-flop, when one of the output signals is of logic “1”, the other output signal is of logic “0”. Consequently, the output signal from NAND gate 221 ₀ and the output signal from NAND gate 221 ₁ can be used as a switching signal for switching between the active system and the backup system.

If switch managing circuit (#0) 220 ₀ is in the active state in the active system configuration, the output signal from NAND gate 221 ₀ is of logic “0” and the output signal from NAND gate 221 ₁ is of logic “1”, putting switch managing circuit (#1) 220 ₁ in the standby state. In this state, when an alarm is generated in switch managing circuit (#0) 220 ₀, one of the input signals of NAND gate 221 ₀ becomes logic “0”, and the output signal of NAND gate 221 ₀ becomes logic “1”. As all the input signals of NAND gate 221 ₁ become logic “1”, the output signal of NAND gate 221 ₁ becomes logic “0, returning logic “0” to NAND gate 221 ₀. Therefore, the output signal of NAND gate 221 ₀ is fixed to logic “1”. Switch managing circuit (#0) 220 ₀ wherein the alarm is generated changes from the active state to the standby state, and switch managing circuit (#1) 220 ₁ changes from the standby state to the active state.

If either one of logic processors (#0, #1) 200 ₀, 200 ₁ as highway cards is pulled out, the switch managing circuit of the remaining logic processor is automatically put into the active state. Specifically, it is assumed that logic processor (#0) 200 ₀ is pulled out when switch managing circuit (#0) 220 ₀ is in the active state and switch managing circuit (#1) 220 ₁ is in the standby state. Though input terminal Y of selector 223 ₁ of switch managing circuit (#1) 220 ₁ becomes open, a signal of logic “1” is applied to input terminal Y by pull-up resistor 224 ₁. Since the signal of logic “1” is applied to NAND gate 221 ₁, the output signal of NAND gate 221 ₁ becomes logic “0”, changing switch managing circuit (#1) 220 ₁ from the standby state to the active state.

For manually switching switch managing circuits (#0, #1) 220 ₀, 220 ₁ between the active system and the backup system, a negative pulse is input to an input terminal of NAND gate 221 ₀ or NAND gate 221 ₁. It is assumed that a negative pulse is input to an input terminal of NAND gate 221 ₀ when switch managing circuit (#0) 220 ₀ is in the active state and switch managing circuit (#1) 220 ₁ is in the standby state. The output signal of NAND gate 221 ₀ temporarily becomes logic “1”, applying an input signal which is temporarily of logic “1” to NAND gate 221 ₁ through selector 223 ₁. The output signal of NAND gate 221 ₁ temporarily becomes logic “0” and is returned through selector 223 ₀ to the input terminal of NAND gate 221 ₀. Therefore, the output signal of NAND gate 221 ₀ is fixed to logic “1”. Switch managing circuit (#0) 220 ₀ changes from the active state to the standby state, and switch managing circuit (#1) 220 ₁ changes from the standby state to the active state.

Operation of Switching Circuits (#0, #1) 310 ₀, 310 ₁:

Operation of switching circuits (#0, #1) 310 ₀, 310 ₁ when the layer 2 switch switching circuit is incorporated in the active-backup system will be described below with reference to FIGS. 2 and 5.

Selectors 311 ₀, 313 ₀ of switching circuit (#0) 310 ₀ and selectors 311 ₁, 313 ₁ of switching circuit (#1) 310 ₁ select respective input terminals Y when process setting switch 700 sets the layer 2 switch switching circuit to the active-backup system configuration.

In switching circuit (#0) 310 ₀, OR circuit 312 ₀ ORs an IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and an IP packet signal from photoelectric transducer circuit (#1) 320 ₁, and inputs a resultant IP packet signal to logic processor (#0) 200 ₀.

In the active-backup system configuration, since an optical fiber transmission path is connected to only one of photoelectric transducer circuit (#0) 320 ₀ and photoelectric transducer circuit (#1) 320 ₁, either one of the IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and the IP packet signal from photoelectric transducer circuit (#1) 320 ₁ is fixed to logic “0”. Therefore, when the IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and the IP packet signal from photoelectric transducer circuit (#1) 320 ₁ pass through OR circuit 312 ₀, only an effective IP packet signal is input to input terminal Y of selector 311 ₀. Thus, OR circuit 312 ₀ performs a function to select an effective IP packet signal out of the IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and the IP packet signal from photoelectric transducer circuit (#1) 320 ₁.

In switching circuit (#0) 310 ₀, OR circuit 314 ₀ ORs an IP packet signal from logic processor (#0) 200 ₀ and an IP packet signal from logic processor (#1) 200 ₁, and inputs a resultant IP packet signal to photoelectric transducer circuit (#0) 320 ₀.

In the active-backup system configuration, either one of the IP packet signal from logic processor (#0) 200 ₀ and the IP packet signal from logic processor (#1) 200 ₁ is fixed to logic “0”. Therefore, OR circuit 314 ₀ performs a function to select an effective IP packet signal out of the IP packet signal from logic processor (#0) 200 ₀ and the IP packet signal from logic processor (#1) 200 ₁.

Similarly, in switching circuit (#0) 310 ₁, OR circuit 312 ₁ ORs an IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and an IP packet signal from photoelectric transducer circuit (#1) 320 ₁, and inputs a resultant IP packet signal to logic processor (#1) 200 ₁.

In the active-backup system configuration, either one of the IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and the IP packet signal from photoelectric transducer circuit (#1) 320 ₁ is fixed to logic “0”, as described above. Therefore, OR circuit 312 ₁ performs a function to select an effective IP packet signal out of the IP packet signal from photoelectric transducer circuit (#0) 320 ₀ and the IP packet signal from photoelectric transducer circuit (#1) 320 ₁.

In switching circuit (#1) 310 ₁, OR circuit 314 ₁ ORs an IP packet signal from logic processor (#0) 200 ₀ and an IP packet signal from logic processor (#1) 200 ₁, and inputs a resultant IP packet signal to photoelectric transducer circuit (#1) 320 ₁.

In the active-backup system configuration, either one of the IP packet signal from logic processor (#0) 200 ₀ and the IP packet signal from logic processor (#1) 200 ₁ is fixed to logic “0”. Therefore, OR circuit 314 ₁ performs a function to select an effective IP packet signal out of the IP packet signal from logic processor (#0) 200 ₀ and the IP packet signal from logic processor (#1) 200 ₁.

The IP packet signal from either one of photoelectric transducer circuit (#0) 320 ₀ and photoelectric transducer circuit (#1) 320 ₁ is transmitted to both logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁, and the IP packet signal from either one of logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁ is transmitted to both photoelectric transducer circuit (#0) 320 ₀ and photoelectric transducer circuit (#1) 320 ₁. Therefore, even though an optical fiber transmission path is connected to either one of photoelectric transducer circuit (#0) 320 ₀ and photoelectric transducer circuit (#1) 320 ₁, an IP packet from the optical fiber transmission path is transmitted to both logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁, and IP packet signals from logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁ are transmitted to the optical fiber transmission path.

Operation of Layer 2 Switches SW (#0, #1) 210 ₀, 210 ₁ and cards (#A Through #C) 100 _(A) Through 100 _(C):

Operation of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ and cards (#A through #C) 100 _(A) through 100 _(C) when the layer 2 switch switching circuit is incorporated in the active-backup system will be described below with reference to FIGS. 2, 3, and 7. For the sake of brevity, only operation of cards (#A, #B) 100 _(A), 100 _(B) will be described below.

One of layer 2 switches SW (#0, #1) 210 ₀, 210 ₁ is in the active state (ACT), and the other in the standby state (STBY) state. One of the signals on signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁ is active, and the other inactive.

Operation of the layer 2 switch switching circuit for switching between the active system and the backup system due to a fault of layer 2 switch SW (#0) 210 ₀ when layer 2 switch SW (#0) 210 ₀ is in the active state and layer 2 switch SW (#1) 210 ₁ is in the standby state will be described below. It is assumed that transmitting conditions of signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁, card (#A) 100 _(A), and card (#B) 100 _(B) are the same as those of the dual active system configuration.

Operation of the layer 2 switch switching circuit for switching between the active system and the backup system when layer 2 switch SW (#0) 210 ₀ is in the active state and layer 2 switch SW (#1) 210 ₁ is in the standby state will be described below with reference to the timing chart shown in FIG. 7.

Prior to time T1, layer 2 switch SW (#0) 210 ₀ is in the active state (ACT) and layer 2 switch SW (#1) 210 ₁ is in the standby state (STBY). Therefore, state signal delivery unit 213 ₀ is delivering an active signal to signal line SW_CONT#0B 501 ₀, and state signal delivery unit 213 ₁ is delivering an inactive signal to signal line SW_CONT#1B 501 ₁. Buffer state signal delivery unit 214 ₀ is delivering a signal indicating that internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ is holding IP packets to signal line SW_EMP#0B 502 ₀. Both card controllers 101 of card (#A) 100 _(A) and card (#B) 100 _(B) are sending IP packets to layer 2 switch SW (#0) 210 ₀. Switch controller 211 ₀ of layer 2 switch SW (#0) 210 ₀ is sending IP packets to a corresponding one of card (#A) 100 _(A) and card (#B) 100 _(B). Switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ is not sending IP packets as layer 2 switch SW (#1) 210 ₁ is in the standby state.

When the user sets logic processor (#0) 200 ₀ to the closure state at time T1, a state instruction signal indicative of the standby state is input from switch managing circuit (#0) 220 ₀ to layer 2 switch SW (#0) 210 ₀. Then, state signal delivery unit 213 ₀ of layer 2 switch SW (#0) 210 ₀ immediately makes the signal on signal line SW_CONT#0B 501 ₀ inactive. A state instruction signal indicative of the active state is input from switch managing circuit (#1) 220 ₁ to layer 2 switch SW (#1) 210 ₁. Then, state signal delivery unit 213 ₁ of layer 2 switch SW (#1) 210 ₁ immediately makes the signal on signal line SW_CONT#1B 501 ₁ active.

Between time T1 and time T2, in response to the inactive signal on signal line SW_CONT#0B 501 ₀, card controller 101 of each of card (#A) 100 _(A) and card (#B) 100 _(B) monitors signal line SW_CONT#1B 501 ₁. Since the signal on signal line SW_CONT#1B 501 ₁ is active, card controller 101 of each of card (#A) 100 _(A) and card (#B) 100 _(B) sends IP packets to layer 2 switch SW (#1) 210 ₁.

Switch controller 211 ₀ of layer 2 switch SW (#0) 210 ₀ continuously sends IP packets held by internal buffer 212 ₀ until it completes the transmission of all the IP packets held by internal buffer 212 ₀. When switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ detects the transition of layer 2 switch SW (#0) 210 ₀ to the standby state based on the signal on signal line SW_CONT#0B 501 ₀, switch controller 211 ₁ accepts IP packets from card (#A) 100 _(A) and card (#B) 100B and holds them in internal buffer 212 ₁, but stops sending IP packets to card (#A) 100 _(A) and card (#B) 100 _(B). Switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ monitors signal line SW_EMP#0B 502 ₀, and waits until the transmission of all the IP packets held by internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ is completed and internal buffer 212 ₀ becomes empty.

When internal buffer 212 ₀ of layer 2 switch SW (#0) 210 ₀ becomes empty at time T2, switch controller 211 ₁ of layer 2 switch SW (#1) 210 ₁ resumes sending IP packets held by internal buffer 212 ₁. At this time, layer 2 switch SW (#0) 210 ₀ completely changes to the standby state (STBY).

According to the present embodiment, as described above, cards (#A through #C) 100 _(A) through 100 _(C) monitor whether layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ are in the active state or the standby state, based on the state signals transmitted through signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁, and switches the destination of IP packets to layer 2 switch SW (#0) 210 ₀ or layer 2 switch SW (#1) 210 ₁ depending on the monitored result.

Consequently, when both layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ are in the active state in the dual active system configuration, even if one of the layer 2 switches is put into the standby state, cards (#A through #C) 100 _(A) through 100 _(C) can automatically switch the destination of IP packets from the layer 2 switch that is put into the standby state to the layer 2 switch that is continuously in the active state. Therefore, the active state of both layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ can switch to the active state of one of layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁.

Furthermore, when layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ are in the active-backup system configuration with one of them in the active state and the other in the standby state, if the layer 2 switch in the active system changes from the active state to the standby state, cards (#A through #C) 100 _(A) through 100 _(C) can automatically switch the destination of IP packets from the layer 2 switch that is in the active state to the layer 2 switch that is in the standby state. Therefore, layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ can switch between the active system and the backup system.

As described above, regardless of whether the redundant configuration is either the dual active system configuration or the active-backup system configuration, the destination of IP packets from cards (#A through #C) 100 _(A) through 100 _(C) can be switched without the need for a dedicated device which has heretofore been required. Since the destination of IP packets from cards (#A through #C) 100 _(A) through 100 _(C) can be switched in either the dual active system configuration or the active-backup system configuration, the layer 2 switch switching circuit according to the present invention is compatible with both the dual active system configuration and the active-backup system configuration.

According to the present embodiment, layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ monitor whether the companion layer 2 switch is in the active state or the standby state based on the signals transmitted through signal line SW_CONT#0B 501 ₀ and signal line SW_CONT#1B 501 ₁. If the layer 2 switch detects when the companion layer 2 switch changes from the active state to the standby state, the layer 2 switch stops sending IP packets. The layer 2 switch resumes sending IP packets when the transmission of all the IP packets held by the internal buffer of the companion layer 2 switch is completed.

Even when layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ detect when the companion layer 2 switch changes from the active state to the standby state, they wait until the transmission of all the IP packets held by the internal buffer of the companion layer 2 switch is completed. Therefore, it is possible to prevent a packet loss from occurring which would be caused if past IP packets remain in the companion layer 2 switch. As a packet loss is prevented from occurring, it is not necessary to send at all times replicas of IP packets from the layer 2 switch from which the destination of IP packets is to be switched to the layer 2 switch to which the destination of IP packets is to be switched, and hence a duplication of IP packets is avoided. Furthermore, because layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ resume sending IP packets after the transmission of all the IP packets held by the internal buffer of the companion layer 2 switch is completed, the sequence of IP packets sent to cards is prevented from being scrambled.

In the present embodiment, process setting switch 700 is installed as being independent of each of the cards. However, process setting switch 700 may be installed in each card. If process setting switch 700 is installed in some of the cards only, then those cards need to be installed under different conditions from the other cards. It is thus not preferable to install process setting switch 700 in some of the cards only from the standpoint of production of the cards. Based on the premise that the cards are identical in structure, two process setting switches 700 may be installed respectively in logic processor (#0) 200 ₀ and logic processor (#1) 200 ₁, and the output signals from process setting switches 700 may be wired-ORed to provide a single setting signal. In this case, two process setting switches 700 should have the same settings at all times.

In the present embodiment, when layer 2 switch SW (#0) 210 ₀ changes from the active state to the standby state, packets held in layer 2 switch SW (#0) 210 ₀ are distributed to the cards by layer 2 switch SW (#0) 210 ₀ itself. However, packets held in layer 2 switch SW (#0) 210 ₀ may be distributed to the cards by layer 2 switch SW (#1) 210 ₁. In this case, dedicated Ethernet link 503 is connected between layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁, and when layer 2 switch SW (#0) 210 ₀ changes from the active state to the standby state, a reading circuit (not shown) in layer 2 switch SW (#0) 210 ₀ reads all IP packets held in layer 2 switch SW (#0) 210 ₀, and layer 2 switch SW (#1) 210 ₁ acquires all the read IP packets and distributes them to the cards. With this arrangement, even if layer 2 switch SW (#0) 210 ₀ suffers a fault of a substantial scale and has difficulty sending IP packets held in layer 2 switch SW (#0) 210 ₀ by itself, it is possible to switch between the layer 2 switches for distributing IP packets without causing a packet loss.

In the present embodiment, the layer 2 switch switching circuit has signal line SW_EMP#0B 502 ₀ and signal line SW_EMP#1B 502 ₁ between layer 2 switch SW (#0) 210 ₀ and layer 2 switch SW (#1) 210 ₁ for indicating that the internal buffer of the companion layer 2 switch is empty. However, some switch devices serving as layer 2 switches are unable to monitor whether the internal buffer is empty or not. With such switch devices, a maximum transmission time required until the transmission of all the packets held by the internal buffer of the companion layer 2 switch is completed is calculated in advance based on the maximum storage capacity of the internal buffer, and when the maximum transmission time elapses after the companion layer 2 switch has changed to the standby state, IP packets held by the internal buffer start being sent out regardless of the number of those IP packets. The sequence of IP packets is thus prevented from being scrambled.

While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims. 

1. A layer 2 switch switching circuit comprising: two layer 2 switches of a redundant configuration; and a plurality of cards for sending IP packets to each other through either one of said two layer 2 switches; each of said two layer 2 switches having a state signal delivery unit for delivering a state signal representing whether the layer 2 switch is in an active state or a standby state; each of said cards having a card controller for monitoring states of said two layer 2 switches based on state signals sent respectively from said two layer 2 switches, and switching between said two layer 2 switches as a destination of IP packets based on the monitored states.
 2. A layer 2 switch switching circuit according to claim 1, wherein each of said two layer 2 switches further comprises: an internal buffer for temporarily storing IP packets; and a switch controller for monitoring the state of the other layer 2 switch based on the state signal delivered from the other layer 2 switch, stopping sending IP packets to the corresponding card when a transition of the other layer 2 switch from the active state to the standby state is detected, and resuming sending IP packets to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.
 3. A layer 2 switch switching circuit according to claim 2, wherein if said switch controller receives IP packets from said cards while said switch controller is stopping sending IP packets to the corresponding card when the transition of the other layer 2 switch from the active state to the standby state is detected, said switch controller stores the received IP packets in said internal buffer, and said switch controller resumes sending the IP packets stored in said internal buffer to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.
 4. A layer 2 switch switching circuit according to claim 2, wherein each of said two layer 2 switches further comprises: a buffer state signal delivery unit for delivering a buffer state signal representing whether said internal buffer is storing IP packets or not; wherein said switch controller determines whether the other layer 2 switch has completed sending all IP packets held by the internal buffer thereof or not, based on the buffer state signal delivered by said buffer state signal delivery unit of the other layer 2 switch.
 5. A layer 2 switch switching circuit according to claim 2, wherein said switch controller calculates in advance a maximum transmission time required for the other layer 2 switch to complete sending all IP packets held by the internal buffer thereof, based on a maximum storage capacity of the internal buffer of the other layer 2 switch, and determines whether the other layer 2 switch has completed sending all IP packets held by the internal buffer thereof or not, depending on whether said maximum transmission time has elapsed or not when the transition of the other layer 2 switch from the active state to the standby state is detected.
 6. A base station apparatus comprising: two layer 2 switches of a redundant configuration; and a plurality of cards for sending IP packets to each other through either one of said two layer 2 switches; each of said two layer 2 switches having a state signal delivery unit for delivering a state signal representing whether the layer 2 switch is in an active state or a standby state; each of said cards having a card controller for monitoring states of said two layer 2 switches based on state signals sent respectively from said two layer 2 switches, and switching between said two layer 2 switches as a destination of IP packets based on the monitored states.
 7. A base station apparatus according to claim 6, wherein each of said two layer 2 switches further comprises: an internal buffer for temporarily storing IP packets; and a switch controller for monitoring the state of the other layer 2 switch based on the state signal delivered from the other layer 2 switch, stopping sending IP packets to the corresponding card when a transition of the other layer 2 switch from the active state to the standby state is detected, and resuming sending IP packets to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.
 8. A base station apparatus according to claim 7, wherein if said switch controller receives IP packets from said cards while said switch controller is stopping sending IP packets to the corresponding card when the transition of the other layer 2 switch from the active state to the standby state is detected, said switch controller stores the received IP packets in said internal buffer, and said switch controller resumes sending the IP packets stored in said internal buffer to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.
 9. A base station apparatus according to claim 7, wherein each of said two layer 2 switches further comprises: a buffer state signal delivery unit for delivering a buffer state signal representing whether said internal buffer is storing IP packets or not; wherein said switch controller determines whether the other layer 2 switch has completed sending all IP packets held by the internal buffer thereof or not, based on the buffer state signal delivered by said buffer state signal delivery unit of the other layer 2 switch.
 10. A base station apparatus according to claim 7, wherein said switch controller calculates in advance a maximum transmission time required for the other layer 2 switch to complete sending all IP packets held by the internal buffer thereof, based on a maximum storage capacity of the internal buffer of the other layer 2 switch, and determines whether the other layer 2 switch has completed sending all IP packets held by the internal buffer thereof or not, depending on whether said maximum transmission time has elapsed or not when the transition of the other layer 2 switch from the active state to the standby state is detected.
 11. A method of switching between layer 2 switches with a layer 2 switch switching circuit having two layer 2 switches of a redundant configuration, and a plurality of cards for sending IP packets to each other through either one of said two layer 2 switches, comprising the steps of: delivering, from each of said two layer 2 switches, a state signal representing whether said each layer 2 switch is in an active state or a standby state; and monitoring states of said two layer 2 switches based on state signals sent respectively from said two layer 2 switches, and switching between said two layer 2 switches as a destination of IP packets based on the monitored states.
 12. A method according to claim 11, further comprising the steps of: stopping sending IP packets from each of said two layer 2 switches to the corresponding card when a transition of the other layer 2 switch from the active state to the standby state is detected, and resuming sending IP packets to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.
 13. A method according to claim 12, wherein if IP packets are received from said cards while each of said two layer 2 switches is stopping sending IP packets to the corresponding card when the transition of the other layer 2 switch from the active state to the standby state is detected, the received IP packets are stored in said internal buffer, and the IP packets stored in said internal buffer are sent again to the corresponding card when the other layer 2 switch completes sending all IP packets held by the internal buffer thereof.
 14. A method according to claim 12, further comprising the step of: delivering a buffer state signal representing whether said internal buffer is storing IP packets or not, from each of said two layer 2 switches; wherein each of said two layer 2 switches determines whether the other layer 2 switch has completed sending all IP packets held by the internal buffer thereof or not, based on the buffer state signal delivered from the other layer 2 switch.
 15. A method according to claim 12, further comprising the steps of: calculating in advance a maximum transmission time required for the other layer 2 switch to complete sending all IP packets held by the internal buffer thereof, based on a maximum storage capacity of the internal buffer of the other layer 2 switch, and determining whether the other layer 2 switch has completed sending all IP packets held by the internal buffer thereof or not, depending on whether said maximum transmission time has elapsed or not when the transition of the other layer 2 switch from the active state to the standby state is detected. 